The present application is related to a co-pending application entitled METHOD AND SYSTEM FOR INTERRUPT HANDLING USING DEVICE PIPELINED PACKET TRANSFERS, Application Ser. No. 09/224,111, filed on even date herewith and xe2x80x9cPIPELINED READ TRANSFERSxe2x80x9d, previously filed and now issued as U.S. Pat. No. 6,240,474 on May 29, 2001, both application and patent assigned to the assignee of the present application.
1. Technical Field
The present invention relates generally to information processing systems and more particularly to an improved information transfer methodology in a computer-related environment. Still more particularly, the present invention relates to a method and system for input/output device read transfers that utilize a request phase and a response phase in association with the systems interrupt controller.
2. Description of the Related Art
As computer systems and networked computer systems proliferate, and become integrated into more and more information processing systems which are vital to businesses and industries, there is an increasing need for faster information processing and increased data handling capacity. Even with the relatively rapid state-of-the-art advances in processor technology, and the resulting increased processor speeds, a need still exists for faster processors and increased system speeds and more efficient information processing methodologies. This need is at least partially due to a growing number of computer applications and capabilities, including extensive network and rich graphics and display applications among others. As new applications for computers are implemented, new programs are developed and those programs are enriched with new capabilities almost on a daily basis. While such rapid development is highly desirable, there is a capability cost in terms of system speed.
One of the problems that have been difficult to solve with the rapid growth of computer data or information-processing systems is the complexity of interrupts from I/O devices. There are a number of problems that need to be solved simultaneously relative to interrupts, more specifically, scalability, data coherency, latency and how to connect far removed remote input/output devices. In terms of scalability, the problem is in how to scale from a small number of devices to a large number without incurring larger than necessary costs at the low end or limiting the number of interrupting devices at the high end. The problem encountered in data coherency is how to assure that the interrupt is not serviced by the system before the data is at its destination. In today""s computer systems, the I/O device transfers the data through host bridges and the like and signals that the operation is complete through a separate path. If this separate path is faster than the path that the data takes, then the interrupt could be serviced before the data is at the destination, and wrong data could be accessed.
The problem inherent in latency is how to reduce the service time and overhead of a device interrupt. If the latency to access the I/O device to gather status or reset interrupts is large, then the interrupt service time is extended, affecting the amount of useful work that the system can perform. Lastly, with respect to remote input/output (I/O) devices, a problem exists is how to interconnect the interrupts from I/O devices that may be located across cables or fiber optic links (a very real possibility because all the I/O in large systems may not fit inside a relatively small box).
Running separate wires from each I/O device to some centrally located interrupt controller may not be feasible.
In the past, there have been a number of attempts to solve some of these problems individually.
Therefore, there is a need for an improved information processing methodology and system in which information is more efficiently transferred between master and target devices during information processing transactions and which offers a global solution to all the problems stated above. This invention solves these problems in a novel and unique manner that has not been part of the art previously.
It is therefore one object of the present invention to provide a method and system for scaling from a small number of devices to a large number without incurring larger than necessary costs at the low end or limiting the number of interrupting devices at the high end.
It is another object of the present invention to provide a method and system in which information is more efficiently transferred by increasing data coherency and reducing latency between master and target devices during information processing transactions.
It is still yet another object of the present invention to provide a method and system in which interrupts can be may be transferred from a remotely attached I/O device.
The foregoing objects are achieved as is now described. A method and apparatus is provided in which Pipelined Packet Transfers (PPT) are implemented. The PPT methodology includes a request phase and a response phase. The PPT request phase involves a PPT request master delivering to a PPT request target a source address, a destination address and an information packet for the interrupt being requested. The PPT response phase involves the PPT request target becoming a PPT response master with the PPT response master delivering to a PPT request master a destination address and a data packet which includes the interrupt processing information. Pipelined Packet transfers (PPT) are ordered in accordance with a predetermined processing priority to improve performance and avoid deadlock.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.